We propose synergistic software and hardware mechanisms that alleviate the address translation overhead, focusing particularly on virtualized execution. On the software side, we propose contiguity-aware (CA) paging, a novel physical memory allocation technique that creates larger-than-a-page contiguous mappings while preserving the flexibility of demand paging. CA paging applies to the hypervisor and guest OS memory manager independently, as well as to native systems. Moreover, CA paging benefits any address translation scheme that leverages contiguous mappings. On the hardware side, we propose SpOT, a simple micro-architectural mechanism to hide TLB miss latency by exploiting the regularity of large contiguous mappings to predict address translations in both native and virtualized systems. We implement and emulate the proposed techniques for the x86-64 architecture in Linux and KVM, and evaluate them across a variety of memory-intensive workloads. Our results show that: (i) CA paging is highly effective at creating vast contiguous mappings, even when memory is fragmented, and (ii) SpOT exploits the created contiguity and reduces address translation overhead of nested paging from ∼16.5% to ∼0.9%.



June, 2020


  • Chloe Alverti
  • Stratos Psomadakis
  • Vasileios Karakostas
  • Jayneel Gandhi
  • Konstantinos Nikas
  • Georgios Goumas
  • Nectarios Koziris

Research Areas

  • Computer Architecture
  • Operating Systems
  • Virtual Memory




International Symposium on Computer Architecture (ISCA)